FPGAs are silicon devices that can be dynamically reprogrammed with a datapath that exactly matches your workloads, such as data analytics, image inference, encryption, and compression. This versatility enables the provisioning of a faster processing, more power efficient, and lower latency service – lowering your total cost of ownership, and maximizing compute capacity within the power, space, and cooling constraints of your data centers.


EulerProject’s accelerators allow customers to combine the OpenCL FPGA programming model with IntelFPGA massively parallel FPGA architecture. This combination enables dramatic acceleration of compute intensive applications while reducing power consumption and total cost of ownership.

Gzip Compression EulerLine

Gzip is a widely used compression and decompression method.

EulerProject presents a compression implementation on EulerLine FPGA accelerator using Intel® FPGA SDK for OpenCL™ that demonstrates:

  • Highly competitive performance against CPU, register transfer level (RTL), and ASIC implementations: 2.84 GBps
  • Significant productivity boost compared to RTL or ASIC implementations: OpenCL implementation completed in one month

Details about the implementation and results can be found in the paper Gzip on a Chip: High Performance Lossless Data Compression on FPGAs using OpenCL, which was presented as part of the International Workshop on OpenCL 2014.

Embedded FPGAs Offer SoC Flexibility

The IP cores offer system-on-chip (SoC) designers an ability to create hardware accelerators and to support changing algorithms. Proponents claim the approach provides advantages to artificial intelligence (AI) processors, automotive ICs, and the SoCs used in data centers, software-defined networks, 5G wireless, encryption, and other emerging applications.

With mask costs escalating rapidly, eFPGAs offer a way to customize SoCs without spinning new silicon. While eFPGAs cannot compete with custom silicon in terms of die area, the flexibility, speed, and power consumption are proving attractive. eFPGAs to be a very profound development in any industry, a capability that is going to get used in lots of places that we haven’t even imagined yet.

FPGAs Beat GPUs in Accelerating Next-Generation Deep Learning

Continued exponential growth of digital data of images, videos, and speech from sources such as social media and the internet-of-things is driving the need for analytics to make that data understandable and actionable.

Data analytics often rely on machine learning (ML) algorithms. Among ML algorithms, deep convolutional neural networks (DNNs) offer state-of-the-art accuracies for important image classification tasks and are becoming widely adopted.

Deep learning is the most exciting field in AI because we have seen the greatest advancement and the most applications driven by deep learning. While AI and DNN research favors using GPUs, we found that there is a perfect fit between the application domain and Intel’s next generation FPGA architecture. We looked at upcoming FPGA technology advances, the rapid pace of innovation in DNN algorithms, and considered whether future high-performance FPGAs will outperform GPUs for next-generation DNNs. Our research found that FPGA performs very well in DNN research and can be applicable in research areas such as AI, big data or machine learning which requires analyzing large amounts of data. The tested Intel Stratix 10 FPGA outperforms the GPU when using pruned or compact data types versus full 32 bit floating point data (FP32). In addition to performance, FPGAs are powerful because they are adaptable and make it easy to implement changes by reusing an existing chip which lets a team go from an idea to prototype.

Microsoft has been deploying FPGAs in every Azure server over the last several years, creating a cloud that can be reconfigured to optimize a diverse set of applications and functions. This configurable cloud provides more efficient execution than CPUs for many scenarios without the inflexibility of fixed-function ASICs at scale. Today, Microsoft is already using FPGAs for Bing search ranking, deep neural network (DNN) evaluation, and software defined networking (SDN) acceleration. Azure’s FPGA-based accelerated networking reduces inter-virtual machine latency by up to 10x while freeing CPUs for other tasks. We describe Microsoft’s cloud FPGA architecture, show how these applications are using it, show live demos of the performance that FPGAs provide, and discuss possible uses.

Accelerating the IoT with Intel® FPGAs and SoCs

IoT promises to be a broad driving force that will create significant new innovation, facilitate new business models and improve global society in unimaginable ways. Intel FPGA (formerly Altera®) solutions enable true flexibility and scalability to address IoT requirements; inherent hardware programmability and software programmability. This powerful combination allows you to enable autonomous operation, tailor your solution to your customer's specific requirements and scale solutions to meet fragmented and evolving market requirements.

From intelligent buildings and connected cars to smart power grids and city infrastructure, FPGAs democratize IoT innovation. Our solutions enable anyone to develop any application, scaling from single prototype units to hundreds of thousands of units in production. This elegantly mimics the wide variety of different solutions encompassed by IoT rather than a small number of very high volume systems.

Key Benefits of Intel FPGAs and SoCs:

  • Meet fragmented IoT application requirements and optimize yout time-to-market with the flexibility to customize in both hardware and software.
  • Enable inherent, robust security through hardware crypto acceleration and monolithic ARM processor integration.
  • Support diverse and evolving IoT gateway requirements through flexible protocol switching/bridging and secure remote in-field upgrades.
  • Extract maximum value from data analytics at the edge and in the data center with the industry’s highest performance-per-watt and performance-per-$.
  • Preserve R&D investment across a broad portfolio of IoT solutions enabling solutions from things to gateways to the data center.
Intelligent Vision & Video

The ability to incorporate high-definition (HD) video, image processing, analytics, and connectivity has become an essential feature of intelligent vision and video applications.

Computer vision and video capabilities (formerly found only in laboratory settings) are now available: from compact, low-cost, energy-efficient embedded vision systems for automotive, industrial and commercial applications all the way to high-performance computing systems for data center applications.

Intel® FPGAs and SoCs, along with IP cores, development platforms, and a software centric design flow, provide a rapid development path with the flexibility to adapt to evolving challenges and solutions in each part of the video / vision pipeline for a wide range of video and intelligent vision applications.

Flexible Sensor Interfaces

Image sensor suppliers often have proprietary interfaces, and the sensor interfaces keep evolving to keep up with improved sensor capabilities. Intel FPGAs enable designers to adopt new sensor interfaces easily without changing the rest of the design. In contrast, Application Specific Standard Products (ASSPs) require designers to adopt a new ASSP and redesign the camera board.

High Performance Video and Image Signal Processing

Intel FPGAs enable designers todesign high performance video and signal processing systems quickly and flexibly. IP cores such as Intel’s Video and Image Processing (VIP) Suite allow designers to pick and choose video processing functionalities as needed, while the high performance FPGA fabric can be leveraged to accelerate video pre-processing of high resolution videos.

Real-Time Analytics

Intelligent, real-time video analytics are key functions in many vision applications such as automotive driver assistance systems, surveillance, and industrial machine vision, and require complex algorithms such as motion detection, facial recognition, and object detection. With Intel® SoC FPGAs, designers can take advantage of the combined power of the FPGA fabric and the dual-core ARM® Cortex®-A9 hard processor system (HPS) in a single chip. By offloading the computation-intensive functions from the HPS to the FPGA fabric, designers can optimize the implementation of these complex algorithms, thereby improving system performance.

High-Efficiency Video Compression

Highly-efficient compression standards such as H.264/H.265 allow the use of smaller FPGAs to reduce system cost. Moreover, integration of video CODECs with other video processing functions on a single FPGA enables designers to achieve large BOM savings. Intel offers multiple video compression IP cores, which allow designers to flexibly support multiple compression standards and profiles depending on the application requirements.

Application Security Technology Using FPGA and SoCs

Intel® (formerly Altera®) provides a variety of security capabilities to secure your reconfigurable logic designs, system, and data. These capabilities include secure fuse-based and battery-backed root keys, encrypted design bitstream, and other key protection, data erasure, and glitch-protection features.

Intel Stratix® 10 FPGAs and SoCs further enhance these capabilities with a dedicated, glitch-resistant Secure Device Manager, a Physically Unclonable Function for more secure root key and device identity protection, and dedicated hard encryption and authentication accelerators.

Cloud Security

Data clouds and data centers must protect customer and internal data, and must also protect customer virtual instances from interfering with one another. Today's data centers heavily leverage open source software and PKI technology. However, programmable logic solutions can provide additional security in the form of hardware-enforced isolation, hardware identity management, and hardware and Hyperflex accelerated authentication.

Additionally, we provide highly agile bitstream and partial bitstream authentication tools that allow cloud security architects to ensure high integrity, trusted data center solutions.

Data Transaction and Network Security

High-speed packet routers, switches, and enterprise networks are some of the most sought-after targets for malicious and state actors. Although much network management infrastructure is migrating to Software Defined Networks (SDN), many of the high-speed search, sort, and security functions remain in or migrate to dedicated and programmable logic.

Intel FPGAs provide programmable design solutions to accelerate network management, and security solutions for the data backbones of enterprise and infrastructure systems.

Endpoint and Industrial Security

Data communication endpoints—from personal phones and sensors to industrial power and manufacturing equipment—must be secured from malicious commands and data. Intel FPGAs provide hardware command/control logic that is inherently more secure than frequently updated software, and provides multiple strong authentication capabilities in both hard and soft logic. Hardened authenticators are highly resistant to remote attacks, and soft logic authenticators can be implemented in endless redundant and failsafe combinations to meet any level of endpoint security.

Deep Packet Inspection FPGA Solution

Network packet processing applications in the government market must maintain security without abandoning processing power or speed. A customer developing a solution for large-scale deep packet inspection was debating whether to use FPGAs or a multi-core CPU and came to EulerProject after determining that FPGAs provided a better balance of price, power, and performance.

FPGA providing flexibility, performance and integration for tomorrow's T&M systems

The need for testing is a requirement of all market segments. Regardless of the end market, all products have to be tested before being shipping to the end-customer. This dynamic drives the pervasive nature of the test and measurement segment, which includes the following categories and sub-segments:

Communication Test

  • Wireless Testers (WiMax, WiFi)
  • Wireline Testers (Ethernet)
  • Optical Testers
  • Traditional Telco Field Testers

Semiconductor ATE

  • Digital Testers
  • Analog/RF Testers
  • Mixed Signal
  • Memory Testers
  • System-on-a-Chip (SoC) Testers

General-Purpose Test

  • Oscilloscopes
  • Signal Generators & Analyzers
  • Logic Analyzers
  • Multimeters & Counters
  • Automotive Testers
Digital Signal Processing (DSP)

Technological breakthrough allows the variable-precision DSP blocks to be configured at compile time into the IEEE 754 floating-point, standard-precision (18 bit), or high-precision (27 bit) mode. In floating-point mode, each DSP block provides a single-precision multiplier and single-precision adder enabling DSP designers with the following key benefits:

  • Shortened development time: Using FPGAs with native floating-point operators eliminates the need to convert your floating-point designs to fixed-point designs, overcoming an already challenging and lengthy task. The productivity advantages of not having to convert to fixed-point design are further amplified as you iterate your design.
  • Improved floating-point performance: Past floating-point implementations were limited in performance due to timing bottlenecks by additional logic and routing resources required to implement floating-point operators. With native support for floating point in the new variable-precision digital signal processing (DSP) blocks, floating-point operations can run at the frequency of the DSP blocks, delivering significantly higher performance.
  • Higher resource efficiency: Past floating-point implementations required additional logic and routing resources, large complex floating-point designs would run out of logic before DSP blocks. DSP blocks with hardened floating point allow designers to fully utilize all floating-point operators in all of the DSP blocks while lowering power and enabling more logic to be available for additional features and functions.
FPGA Solutions for High Frequency Trading

Financial Application Challenges With high frequency trades being executed in microseconds, the ability to minimize the delay between market data arrival and issuing the trade is key. High frequency trading applications must account for a variety of challenges. These applications require ultra-low latency feed handling as well as ever-faster analysis/ data correlation. They should also attain maximum performance per watt to minimize energy and thermal requirements. Many applications also require a scalable architecture to enable “FPGA Farm” implementation. EulerProject offers FPGA-based PCIe COTS solutions to address the challenges of developing applications for the financial acceleration/HFT (High Frequency Trading) market.

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