Portable FPGA Acceleration OpenCL Workstation

Basic Workstation controls

The composition of the Workstation

Euler Line Accelerator

- FPGA: 10AX115H4F34 - 1150K LE, 12.5Gbit li>
- Arria 10 GX FPGA Array of Logic: li>
- LEs (K): 1150 ALMs: 427 200 li>
- Memory M20K: 54,260 li>
- Memory MLAB: 12,984 li>
- DSP blocks: 1518 li>
- 18x19 Multiplier: 3036 li>
- Performance: up to 1.5 Tflops li>
- LINK: PCIe Gen. 2/3 x8 lanes li>
- MEMORY HILO: 4GB-DDR4 / 4GB-DDR3 / QDRIV / RLDRAM / Custom li>
- MEMORY: DDR4 SO-DIMM 8 - 16GB li>
- NETWORK: 1Gb RJ45, 2x10Gb SFP + li>
- Board sizes: PCIe card half size li>
- Compatibility with Intel OpenCL Compiler, BSP li>
Lagrange Pico-ITX motherboard

- Designed and manufactured in Russia li>
- Qseven 1.2 and 2.0 modular platform li>
- AMD System-on-Chip li> CPU
- 2.0 GHz CPU li>
- 4 x86 cores li>
- 2 MB L2 Cache li>
- TDP 25 W li>
- Integrated video GPU HD 8400E 600MHz li>
- 2-4GB DDR3-1600 RAM li>
- STM32 Programmable Controller li>
- USB 2.0 connectors: 4 onboard, 2 external li>
- Ethernet 1G connector li>
- HDMI connector li>
- PCIe, mini PCIe, mSata slot li>
- External connectors: 2x RS232, CAN li>
- Compact Pico-ITX form factor (100x72 mm) li>
Software

- OC CentOS Linux li>
- IntelFPGA Run-time Environment li>
- Euler Line OpenCL BSP Package li>
- Test example algorithm based on DES, implementation on OpenCL: li>
- 20 asynchronous cores li>
- up to 25 million combinations / c li>