Portable FPGA Acceleration OpenCL Workstation
Basic Workstation controls
The composition of the Workstation
Euler Line Accelerator
- FPGA: 10AX115H4F34 - 1150K LE, 12.5Gbit
- Arria 10 GX FPGA Array of Logic:
- LEs (K): 1150 ALMs: 427 200
- Memory M20K: 54,260
- Memory MLAB: 12,984
- DSP blocks: 1518
- 18x19 Multiplier: 3036
- Performance: up to 1.5 Tflops
- LINK: PCIe Gen. 2/3 x8 lanes
- MEMORY HILO: 4GB-DDR4 / 4GB-DDR3 / QDRIV / RLDRAM / Custom
- MEMORY: DDR4 SO-DIMM 8 - 16GB
- NETWORK: 1Gb RJ45, 2x10Gb SFP +
- Board sizes: PCIe card half size
- Compatibility with Intel OpenCL Compiler, BSP
Lagrange Pico-ITX motherboard
- Designed and manufactured in Russia
- Qseven 1.2 and 2.0 modular platform
- AMD System-on-Chip CPU
- 2.0 GHz CPU
- 4 x86 cores
- 2 MB L2 Cache
- TDP 25 W
- Integrated video GPU HD 8400E 600MHz
- 2-4GB DDR3-1600 RAM
- STM32 Programmable Controller
- USB 2.0 connectors: 4 onboard, 2 external
- Ethernet 1G connector
- HDMI connector
- PCIe, mini PCIe, mSata slot
- External connectors: 2x RS232, CAN
- Compact Pico-ITX form factor (100x72 mm)
Software
- OC CentOS Linux
- IntelFPGA Run-time Environment
- Euler Line OpenCL BSP Package
- Test example algorithm based on DES, implementation on OpenCL:
- 20 asynchronous cores
- up to 25 million combinations / c