PARALLEL COMPUTING WITH FPGA ACCELERATION

• An FPGA is an advanced, user-customizable, multi-function accelerator for both, Embedded and Heterogeneous Computing Systems

• The flexibility of an FPGA allows users to create highly differentiated products

• An FPGA’s functions can be reprogrammed as market dynamics change or standards evolveheterogeneous host accelerator computing system is being built.

In combination with CPUs or standalone, the high-performance and low-energy requirements make FPGAs an attractive choice for integration into computing systems and products. Because FPGAs are easily configurable, system designers can change the function of devices into which they’re installed. In fact, FPGAs can become ‘custom silicon’ and can change system behavior dynamically. FPGAs can also be fine-tuned in order to upgrade performance, update security settings, and modify for individual or local needs.

EulerProject design and produce FPGA Reconfigurable Acceleration Products for Data Center, Video Analytics, Telecom and IoT industry


Consider our platforms when you are at:

Your technologies will need to translate this enormous supply of data into intelligence. Translating data into intelligence will require various high-level processing capabilities, including pattern recognition, encryption and decryption, big data compression, and big data analysis.

Your computing are not yet up to speed and it seems, that your software currently exceeds the abilities of hardware, which can lead to bottlenecks in data flows. Your are up to faster processing, and this could includes offloading CPUs to FPGAs

You are also aware of the FPGAs challenges with difficulties in HDL design flow and would consider high level development and more standardized implementation. To better handle these challenges, you would consider to integrate into your product or system "Off-the-shelf" FPGA board (COTS board) with standard open programming model and get deep technical support.

Your systems and operating budgets are limited by power. FPGAs and ASICs offer superior performance per watt footprint, but only the FPGA is dynamically reconfigurable.

EMBEDDED SYSTEMS
SoC SoMs are small, integrated single-board computers with Cyclone® V SoCs at the core. The SoC SoM includes DDR3 memory, flash memory, power management, common interface controllers, and OpenCL board support package (BSP) software to help you create a fully customized embedded design without starting from scratch.

HPS system:
  • CPU: 800-MHz, dual-core ARM® Cortex™-A9 MPCore™ processor
  • SD/SDIO/MMC controller with DMA
  • 2x 10/100/1000 Ethernet media access control (MAC) with DMA
  • 2x USB On-The-Go (OTG) controller with DMA
  • 2x I2C controller
  • 2x UART
  • 2x serial peripheral interface (SPI)
  • Up to 134 general-purpose I/O (GPIO)
  • 7x general-purpose timers
  • 4x watchdog timers
FPGA system:
  • LEs(K): 25 - 110
  • ALMs: 9,434 - 41,509
  • M10K memory blocks: 140 - 514
  • M10K memory (Kb): 1,400 - 5,140
  • MLABs (Kb): 138 - 621
  • 18-bit x 19-bit multipliers: 72 - 224
SDRAM MEMORY:
  • DDR3-400MHz 256MB / 512MB / 1GB
FLASH:
  • NAND FLASH 128MB / 256MB / 512MB
  • QSPI FLASH 8MB / 16MB / 32MB
SoM size:
  • 54 x 44мм
Software support:
  • Firmware with U-BOOT, Linux kernel, RootFS image.
  • OpenCL BSB with video-channel is available.
OPENCL PARALELL COMPUTING EDUCATION PLATFORM
Intel 10AX115 Full-Size FPGA PCIe accelerator with Windows/Linux OpenCL BSP support and FMC extensions

  • PCIe full-size, Gen 3.0 x 8
  • Up to 1.5 TFLOPS per card
  • OpenCL Linux and Windows support, Host-channels support (Linux only)
  • 1.115kLE and 42Мb ultra-fast internal memory
  • 3300 hardware DSP blocks with FPU (IEE754)
  • Global memory: DDR3 /DDR4 (2GB)
  • Optional memory: QDR4 or RLDRAM3
  • Networking: Ethernet 1GE /10GE /40GE
  • Host interface: PCIe Gen 3.0 x 8
  • Two FMC card extension slots
  • Power consumption up to 70W
NETWORKING DATACENTER/TELECOMM PLATFORM
Intel 10AX115 Half-Size PCIe acceleration card with 2х10GE SFP+

  • PCIe Half-size, Gen 3.0 x 8
  • Up to 1.5 TFLOPS per card
  • OpenCL Linux, Host-channels support
  • 1.115kLE and 42Мb ultra-fast internal memory
  • 3300 hardware DSP blocks with FPU (IEE754)
  • Global memory: SODIMM DDR4 (up to 16GB)
  • Optional memory: QDR4 (144Мb)
  • Networking: Ethernet 1GE and 2x10GE SFP+
  • Host interface: PCIe Gen 3.0 x 8
  • Power consumption up to 40W
  • OpenCL BSP (HPC ver. available)
FPGA HIGH PERFORMANCE COMPUTING
Intel 10AX115 Half-Size PCIe Computing acceleration card with 2 independent DDR4 banks

  • PCIe Half-size, Gen 3.0 x 8
  • Up to 1.5 TFLOPS per card
  • OpenCL Linux, Host-channels support
  • 1.115kLE and 42Мb ultra-fast internal memory
  • 3300 hardware DSP blocks with FPU (IEE754)
  • Global memory: 2 banks x DDR4 (up to 8GB each)
  • Host interface: PCIe Gen 3.0 x 8
  • Power consumption up to 40W
  • OpenCL BSP
EMULATION PLATFORM
EulerProject SG 280 FPGA KUB IntelFPGA Stratix-10 Emulation platform
ES is available
Product specs is available on the product webpage
SMART CAMERA AND MACHINE VISION

Euler Smart Camera and Machine Vision Video-kit

  • INTEL CYCLONE-V SOC SOM ON-SEMI VITA 1300 Video-Sensor OPEN-CL BSP VIDEO CAMERALINK
  • PREINSTALLED FIRMWARE (U-BOOT, LINUX KERNEL, ROOTFS IMAGE),
  • OPENCL BSP WITH VIDEO-CHANNEL (CameraLink).
  • OpticalFlow OpenCL example source code
  • Neural Network (SVV and CNN) will be released soon
FPGA OPENCL PORTABLE WORKSTATION

  • Portable workstation with touch-screen
  • Motherboard on AMD CPU
  • FPGA Acceleration EulerLine Network or EulerLine HPC
  • OpenCL BSP HPC

Comparative characteristics

EULER EMBEDDED SOM EULER TREAD EULER LINE NET 2x10GE EULER LINE HPC 2xDDR4E
Operating system Linux Windows Linux Linux
DSP blocks (FPU support) up 112 1518 (FPU IEE754) 1518 (FPU IEE754) 1518 (FPU IEE754)
Internal memory (cache) Mbit, M2K + MLAB 5,1 54+12 54+12 54+12
The possibility of expanding the interfaces and connect devices through ports CameraLink, Ethernet, DVI, USB, SD/MMC, CAN, FMC, I2C, UART 2xFMC, QDR, RLDRAM QDR4 (до 144Мбит) not provided
Memory selection DDR3-400MHz 256МВ / 512МВ / 1GB
NAND FLASH: 128МВ / 256МВ / 512МВ QSPl
QSPI FLASH: 8МВ / 16МВ / 32МВ
DDR3 /DDR4 (2ГБ)
QDR4 (144Mbit)
RLDRAM3 (128МB)
DDR3 SODIMM up (16ГБ)
QDR4 (144МBit)
Two independent banks of DDR4 SODIMM at 16GB each
The computing power of TFLOPS up 1.5 up 1.5 up 1.5
Interface with host Embedded HW dual ARM Cortex-A9 PCIe Gen 2.0, 3.0 x 8 PCIe Gen 2.0, 3.0 x 8 PCIe Gen 2.0, 3.0 x 8 Mechanical PCIe x 16
Ethernet Interfaces 1GE 1GE, 10GE, 40GE 1GE & 2x10GE not provided
Logic capacity, Logic elemens 25, 40, 85, 115 Th LE 1.115 th LE до 1.115 th LE до 1.115 th LE
OpenCL standard support Y Y Y Y
Consumption up to watts per accelerator 3 up 75 up 50 TBD
EULER EMBEDDED SOM EULER TREAD EULER LINE NET 2x10GE EULER LINE NET HPC 2xDDR4
ОС
Linux Windows Linux Linux
DSP blocks (FPU support)
up 112 1518 (FPU IEE754) 1518 (FPU IEE754) 1518 (FPU IEE754)
Internal memory (cache) Mbit, M2K + MLAB
5,1 54+12 54+12 54+12
The possibility of expanding the interfaces and connect devices through ports
CameraLink, Ethernet, DVI, USB, SD/MMC, CAN, FMC, I2C, UART 2xFMC, QDR, RLDRAM QDR4 (up 144Mbit) not provided
Memory selection
DDR3-400MHz 256МВ / 512МВ / 1GB
NAND FLASH: 128МВ / 256МВ / 512МВ QSPl
QSPI FLASH: 8МВ / 16МВ / 32МВ
DDR3 /DDR4 (2ГБ)
QDR4 (144Mbit)
RLDRAM3 (128МB)
DDR3 SODIMM up (16ГБ)
QDR4 (144МB)
Two independent banks of DDR4 SODIMM at 16GB each
The computing power of TFLOPS
up 1.5 up 1.5 up 1.5
Interface with host
Embedded HW dual ARM Cortex-A9 PCIe Gen 2.0, 3.0 x 8 PCIe Gen 2.0, 3.0 x 8 PCIe Gen 2.0, 3.0 x 8 Mechanical PCIe x 16
Ethernet Interfaces
1GE 1GE, 10GE, 40GE 1GE и 2x10GE not provided
Logic capacity, Logic elemens
25, 40, 85, 115 тыс ЛЭ 1.115 th LE 1.115 th LE 1.115 th LE
OpenCL standard support
Y Y Y Y
Consumption up to watts per accelerator
3 up 75 up 50 TBD

Contact Us

Almaz-SP, Open Joint Stock Company 127025, Moscow, Obraztsova str.7, bld 2
+7(495) 221-69-21