EulerProject is official IntelPSG technical training partner for FPGA parallel OpenCL computing and Intel Programmable Acceleration Solutions.
EulerProject team is Gold member of Intel FPGA Design Solutions Network (DSN), with extensive FPGA design experience in PCIe Acceleration Hardware Designs, OpenCL BSP porting and OpenCL application solutions.
We offer the following technical trainings to help our Data-center customers get introduced to efficient FPGA technology, get code writing/optimization skills and learn advanced optimization techniques to result into services acceleration and CPUs offloading with time to market reduction and lower deployment risks.
- • Introduction to Parallel Computing with OpenCL, 1 day/instructor led class
- • OpenCL Programming and Optimization, 1 day/instructor led class
- • Advanced Optimization with OpenCL, 1 day/instructor led class
- • Advanced Optimizations with OpenCL: HDL inference, Host-pipes and Host-channels, 1 day/instructor led class
- • Enabling FPGA Accelerators Using the Acceleration Stack for Intel® Xeon® CPU with FPGAs (coming soon)