TELECOM & NETWORKING

FPGA acceleration for data-intensive processing and networking tasks

CPUs can be packaged with FPGAs, offloading specific tasks to them and enhancing overall data-center and network efficiency. The concept, known as accelerated computing, is increasingly viewed by data-center and network managers as a cost-efficient way to handle increasing data and network traffic

Key applications: Cloud computing and CPU offloading in data centers, big data processing acceleration, machine learning and neural networks, data storage, wireline and wireless telecommunications, DPI, VPN, DDoS, financial analysis and high-frequency trading, digital signal processing, multimedia applications, video-analytics.

GZIP data compression for storage
GZIP-EulerLine

Data compression and recovery using the Gzip algorithm.

Using an FPGA accelerator to compress and recover data significantly improves system bandwidth and performance compared to a powerful processor.

> EulerProject offers the EulerLine accelerator with a prepared GZIP implementation for use in the data center, for example, for the purpose of compressing huge log files.

Fully hardware stand-alone solution, complete unloading of the server CPU.

Embedded Solutions for Video-Analytics and Industrial Automation

Nowadays, image processing and computer vision are widely used in the automation industry. One of the most challenging tasks is the detection and estimationof motion of objects. This can be used in various applications such as driverassistance systems and automation.

The EulerProject Embedded SOM SOC FPGA solution supports OpenCL standard, which provides abstraction level from FPGA design flow and speed-up application developing of embedded video solutions.

Optical Flow Design Example Benchmark: HD X 81 FPS

Our benchmark demonstrates OpenCL FPGA implementation of the Lucas Kanade Optical Flow algorithm.The design example implements a dense, non-iterative, non-pyramidal version with 52x52 window size. It was designed for embedded platforms with smaller FPGA devices, specifically the Cyclone® V SoC.

Neural networks, machine learning

Deep Learning, Machine Learning, intensively using computing resources, are at the forefront of engineering research

EulerProject PCIe accelerators (EulerLine, EulerPrime) supports Intel OpenVino toolkit:

  • Enables deep learning inference from edge to cloud.
  • Accelerates AI workloads, including computer vision, audio, speech, language, and recommendation systems.
  • Speeds up time to market via a library of functions and preoptimized kernels.

Support for accelerating the following video functions is available:

  • Generic Age & Gender Recognition 
  • Camera Tampering Detection 
  • Generic Face Detection 
  • Face Detection for Retail 
  • Person Detection for Retail 
  • Face Detection for Automotive
  • Person, Vehicle & Bike Detection
  • Vehicle License Plate Detection 
  • License Plate Recognition
  • Age & Gender Recognition for Retail
  • Vehicle Attributes Recognition
  • Head Pose Estimation for Automotive
  • Semantic Segmentation
  • Road Segmentation
  • Person Attributes 
  • Person Re-identification
  • Pedestrian Detection
  • Pedestrian & Vehicle Detection
  • Emotions Recognition

More: Euler OpenVino

4G LTE

CPRI Radio-Interface

The Common Public Radio Interface (CPRI) FPGA IP core implements the CPRI Specification V7.0 (2015-10-09). CPRI is a high-speed serial interface for network radio equipment controllers (REC) to receive data from and provide data to remote radio equipment (RE).

The CPRI IP core targets high-performance, remote radio network applications. You can configure the CPRI IP core as an RE or an REC.

The CPRI IP is available for purchasing on EulerLine SFP+, EulerLine QSFP+ FPGA cards.

Network traffic classification acceleration, DPI, DDOS, Smart-NIC

Today, increasing attention is being paid to Data Center (DC) traffic classification since these infrastructures have become the heart of a variety of time-sensitive and data-intensive service platforms. Classification provides the required tools for better understanding traffic patterns in order to ensure high Quality of Service (QoS) performances and solve scalability problems.

EulerProject offers UNIFIED FLOWS FPGA solution for DC traffic filtering & classification:

  • HW platforms: EulerProject PCIe accelerators or MOTS telecom&networking platform
  • 1-10G, 40 G, 100G Ethernet, SDH/SONET, OTN, FibreChannel
  • Maximum packet per sec: 50-200 MPPS.
  • Flexible solution: State less и Stateful DPI with DRAM.
  • Filtering with matrix DPI rules (512-8192).
  • Processing to CPU up to 100 Gbit/s with 16 data queries.
High Performance Computing (HPC)

Accelerating Key-Value Search

  • Processing SIM tables.
  • Speeding up IPv4 and IPv6 addressing handling.
  • NoSQL database acceleration.
  • Search for N-Tuple lookups and Pattern matching cortsages.
  • User and other indicators (UID, ID, SSN, logins).
  • Keyword Search.
  • KVS Search Rate: 10-50 MSPS (searches per second).
  • Capacity of table entries: ~40K in fast internal. memory and ~10M entries in external DDR.
  • Typical string size: 96 bits (12 Bytes) and so on.
  • 100x performance increase to 1000x (compared to CPU).
Prototyping and Emulation, PROFPGA Solutions Distribution

The EulerProject Emulation modules is the logic core for the scalable and modular multi-FPGA solution, which fulfills highest needs in the area of FPGA based Prototyping and Emulation. It addresses customers who need a scalable and most flexible high performance Prototyping solution for early software development and real-time system verification. The innovative KUB system concept and technologies offer highest flexibility and reusability for several projects, which guarantees the best return on invest.

EulerProject (Almaz-SP JSC) is also an official distributor of proFPGA solutions for prototyping and emulation in Russia since 2019.

More
5G L1 offloading

5G L1 Acceleration FlexRAN(vRAN) solution

IP LDPC processing acceleration.

  • 4G Channel Coding Top.
  • TLP Adapter.
  • Queue buffers.
  • DMA and Queue manager.
  • Code Block FIFOs.
  • Load Balancer.
  • Encoder Engine, Decoder Engine.
  • Encoder Chain, Decoder Chain.

IQ compression/decompression IP

  • Decreaselatency-bandwidth.

5G L1 Acceleration solution will be available on EulerLine, EulerPrimeFPGA cards in 2021.

Contact Us

Registered address: 121205, Россия, г. Москва, Территория Сколково инновационного центра, Бульвар Большой, д. 42-1 (Технопарк 3.282)
+7 (495) 181-00-86
https://eulerproject.com/